Efficient FPGA Based Bidirectional Network on Chip Router throgh Virtual Channel Regulator

Abstract

Fundamental unit of building a Network on Chipis the router; it directs the packets according to a routingalgorithm to the desired host. Both NoC performance andenergy budget depend heavily on the routers' bufferresources. This paper introduces a novel BidirectionalNetwork on chip router with unified buffer structure, calledthe dynamic Virtual Channel Regulator, which dynamicallyallocates Virtual Channels (VC) and buffer resourcesaccording to network traffic conditions. In this study, weanalyse the move towards Networks-on-Chips router froman area and power perspective by accurately modeling aBidirectional Network-on-chip router through VirtualChannel Regulator in FPGA. Accurate speed, area andpower metrics are also reported for the networks router,which will allow a more complete comparison to be madeacross the NoC architectural router space considered. Theproposed architecture of BiNoC router is simulated in XilinxISE 9.1i software. We designed a router with scalabilityfeature which is synthesized in models of Virtex-II XC2VP30FPGA infrastructures. The source code is written in VHDL.In addition, the proposed router uses low resource utilizationpercentage of FPGA. From the implementation results, theproposed router is operated with higher speed, area in termsof slices reduced by 38.55% and the LUTs reduced by44.59