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Ultra-low power circuits using graphene p-n junctions and adiabatic computing

Abstract

Recent works have proven the functionality of electrostatically controlled graphene p–n junctions that can serve as basic primitive for the implementation of a new class of compact graphene-based reconfigurable multiplexer logic gates. Those gates, referred as RG-MUXes, while having higher expressive power and better performance w.r.t. standard CMOS gates, they also have the drawback of being intrinsically less power/energy efficient. In this work we address this problem from a circuit perspective, namely, we revisit RG-MUXes as devices that can operate adiabatically and hence with ultra-low (ideally, almost zero) power consumption. More specifically, we show how to build basic logic gates and, eventually, more complex logic functions, by appropriately interconnecting graphene-based p–n junctions as to implement the adiabatic charging principle. We provide a comparison in terms of power and performance against both adiabatic CMOS and their non-adiabatic graphene-based counterparts; characterization results collected from SPICE simulations on a set of representative functions show that the proposed ultra-low power graphene circuits can operate with 1.5–4 orders of magnitude less average power w.r.t. adiabatic CMOS and non-adiabatic graphene counterparts respectively. When it comes to performance, adiabatic graphene shows 1.3 (w.r.t. adiabatic CMOS) to 4.5 orders of magnitude (w.r.t. non-adiabatic technologies) better power-delay product

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PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

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Last time updated on 30/10/2019

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