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Efficient operator pipelining in a bit serial genetic algorithm engine

By Ian Michael Bland and Graham Megson


The authors propose a bit serial pipeline used to perform the genetic operators in a hardware genetic algorithm. The bit-serial nature of the dataflow allows the operators to be pipelined, resulting in an architecture which is area efficient, easily scaled and is independent of the lengths of the chromosomes. An FPGA implementation of the device achieves a throughput of >25 million genes per secon

Publisher: Institution of Engineering and Technology (IET)
Year: 1997
OAI identifier: oai:centaur.reading.ac.uk:4636

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