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Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors

By X. Li, S. Bentley, H. McLelland, M. Holland, H. Zhou, S. Thoms, D.S. Macintyre and I. Thayne

Abstract

This article describes a process flow which has enabled the first demonstration of functional, fully self-aligned, 40 nm gate length replacement gate enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-κ dielectric, Pt/Au metal gate stack, and SiN sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. As a gate replacement approach has been developed, the process is suitable for easily incorporating different gate metals, opening the way to work function engineering to control threshold voltage and so is a significant step forward to the demonstration of high performance “siliconlike” III-V MOSFETs

Publisher: 'American Vacuum Society'
Year: 2010
DOI identifier: 10.1116/1.3501355
OAI identifier: oai:eprints.gla.ac.uk:45325
Provided by: Enlighten
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