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A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols

By J. Dumas, E. Guthmuller, C. Fuguet Tortolero and Frédéric Pétrot


International audienceWith the emergence of manycore processors with potentially hundreds of processors in the embedded market, the scalability of cache coherence protocols is again at stake. One seemingly simple issue is the management of the set of sharers of a memory block, but with that many processors, it is a major bottleneck in terms of hardware resources. In this paper, we define a high level simulation method to evaluate sharing set management strategies, using memory access traces obtained through cycle accurate simulation (e.g.gem5). The goal of the method is to rank protocols based on latency, traffic and hardware cost, to help either choose an existing approach for a given application context, or evaluate new approaches. We demonstrate the applicability of our proposal by evaluating three existing scalable cache coherence protocols, obtaining results consistent with previous, low level, evaluations much more rapidly

Topics: PACS 85.42, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Publisher: 'Springer Fachmedien Wiesbaden GmbH'
Year: 2017
OAI identifier: oai:HAL:hal-01523232v1
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