A VLSI implementation of MIMO detection for future wireless communications
This paper describes a VLSI implementation of V-BLAST detection for future multiple-input-multiple-output (MIMO) wireless communications. This design is implemented using a 0.35-μm 5-layer metal 3.3 V CMOS technology. For a 4-transmit and 4-receive antennas system using QPSK modulation scheme, a detecting throughput of 128 Mb/s can be achieved. Furthermore, it is shown that the implementation complexity can be reduced further to meet the requirements for future high speed downlink packet access (HSDPA) systems with MIMO extensions in 3rd generation (3G) mobile wireless system
Electrical Engineering, Electronic Engineering, Information Engineering, metal CMOS technology, transmit antenna, receive antenna, QPSK modulation scheme, 128 Mbit/s, 3.3 V, 0.35 micron, high speed downlink packet access system, 3G mobile wireless system, vertical-Bell-Labs-layered-space-time detection, VLSI implementation, wireless communication, MIMO detection, multiple-input-multiple-output wireless communication
Publisher: 'Institute of Electrical and Electronics Engineers (IEEE)'
DOI identifier: 10.1109/PIMRC.2003.1259266
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