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A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier

By Pietro Andreani and Lars Sundström

Abstract

This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 mu m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption

Topics: Electrical Engineering, Electronic Engineering, Information Engineering
Publisher: 'Springer Science and Business Media LLC'
Year: 2000
DOI identifier: 10.1023/A:1008315925581
OAI identifier: oai:lup.lub.lu.se:2609572b-de13-44e4-9e72-bafa8c2472f3
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