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Studying The Impact Of Application-level Optimizations On The Power Consumption Of Multi-Core Architectures ∗

By S M Faizur Rahman, Jichi Guo, Akshatha Bhat, Carlos Garcia, Majedul Hoque Sujon, Qing Yi, Chunhua Liao and Daniel Quinlan

Abstract

This paper studies the overall system power variations of two multi-core architectures, an 8-core Intel and a 32-core AMD workstation, while using these machines to execute a wide variety of sequential and multi-threaded benchmarks using varying compiler optimization settings and runtime configu-rations. Our extensive experimental study provides insights for answering two questions: 1) what degrees of impact can application level optimizations have on reducing the overall system power consumption of modern CMP architectures; and 2) what strategies can compilers and application devel-opers adopt to achieve a balanced performance and power efficiency for applications from a variety of science and em-bedded systems domains

Topics: Categories and Subject Descriptors D.3.4 [Software, Programming Languages—Processors [Op- timization, Compilers, C.1.4 [Computer System Orga- nization, Processor Architectures—Parallel Architectures Keywords Power consumption, energy efficiency, application level op- timization, compiler
Year: 2016
OAI identifier: oai:CiteSeerX.psu:10.1.1.1018.3509
Provided by: CiteSeerX
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