A closer look at earlier work on IC defect sensitivities reveals that modeling the geometrical patterns only as conductors can be inaccurate in predicting the probability of failure of the circuit. This way of modeling considers also only one layer at a time and neglects any interrelationships, as is the case with transistors. Furthermore, the only kind of faults covered are of the short and break circuit types. We present a generalization that considers the layout as the union of a set of electrical elements and where depending upon the element the patterns have a significance other than simple conductors. This approach models sensitive areas for a larger coverage of faults including stuck-at transistors and possible performance degradations
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