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High level behavioural modelling of boundary scan architecture.

By Saad Sabih Ahmed Medhat

Abstract

This project involves the development of a software tool\ud which enables the integration of the IEEE 1149.1/JTAG\ud Boundary Scan Test Architecture automatically into an ASIC\ud (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C';\ud ii) A high level model of the Boundary Scan Test\ud Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure.\u

Topics: csi
OAI identifier: oai:eprints.bournemouth.ac.uk:324

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