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The Design and implementfor Transceiver of WIA-PA

By Duan MQ(段茂强), Huang XL(黄晓莉) and Wang JJ(王建军)


In this paper, the system scheme and system architecture for transceiver of WIA-PA are presented. The low-IF topology and direct up conversion method are employed, corresponding to receiver part and transmitter part. And in the baseband part, differential and correlation demodulate received signals, as well as time sync, frequency offset calibrate and frame sync operations are designed for salvation the problem of real radio environmental effects. The chip implements using 0.18m CMOS process has small chip area and low power consumption. The minimum sensitivity of receiver is less than -85dBm for 1% PER (packet error rate), which is better than the required sensitivity for specification

Topics: Wia-pa, Transceiver, Demodulator, Ieee 802.15.4
Publisher: 'Trans Tech Publications, Ltd.'
Year: 2014
DOI identifier: 10.4028/
OAI identifier:
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