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On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

By Roshan Weerasekera, M. Grange, Dinesh B. Pamunuwa and Hannu Tenhunen

Abstract

This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted

Year: 2010
OAI identifier: oai:eprints.lancs.ac.uk:31657
Provided by: Lancaster E-Prints

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Citations

  1. (2001). 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,”
  2. (2004). and D.Edwards, “A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability,” doi
  3. (2007). and J.Kim, “Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation,” in
  4. (1995). and W.Weber, “Interconnect capacitances, crosstalk, and signal delay in vertically integrated circuits,” in
  5. (2007). B.Swinnen, “3D system integration technologies,”
  6. (2008). Enabling technologies for 3D chip stacking,”
  7. (2009). H.Tenhunen, and L.-R.Zheng, “Compact modelling of through-silicon vias (TSVs) in threedimensional (3-D) integrated circuits,” in
  8. (2007). S.Rauf, and R.Chatterjee, “Inter-strata connection characteristics and signal transmission in three-dimensional (3D) integration technology,” in
  9. (2007). Substrate noise coupling in mixed-signal integrated circuits: Compact modeling and grounding strategies,”
  10. (2008). System interconnection design trade-offs in threedimensional integrated circuits,”
  11. (2006). Y.Cao, “New generation of predictive technology model for sub-45nm design exploration,” in

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