A 1.90 GBit/s monolithic comparator implemented on an analog bipolar array


A monolithic comparator with sample rates up to 1.9 Bbit/s integrated on an analog array is presented. The circuit has been implemented on an analog array in a standard bipolar process (fT, NPN = 6.5 GHz). A parallel circuit structure doubles maximum sampling rate

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oaioai:fraunhofer.de:PX-2713Last time updated on 11/15/2016

This paper was published in Fraunhofer-ePrints.

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