ESD in silicon integrated circuits


Chapter Two introduces into phenomena of electrostatic discharge ESD which may damage integrated circuits. It discusses mechanisms generating the electrostatic voltage difference and the short discharge current pulses of high amplitude through the integrated circuit while it is handled either by a person or a machine. Although not dedicated to measures and problems of external ESD control the background helps to understand them and to trace them back to the standard ESD stress models Human Body Model and Charged Device Model. Electrostatic, charge, voltage, current, triboelectric charging, ionic charging, direct charging, field-induced charging, stress model, human body model, charged device model. Chapter Three covers in detail the test methods used for the ESD qualification of integrated circuits and for the pulsed characterization of ESD protection elements during their development. In the context of the ongoing standardization it discusses the test procedures for Human Body Model, Machine Model, Charged Device Model, Socket Device Model and the Transmission Line Pulsing. It deals with the influence of the package and identifies correlation issues including failure criteria and pulse metrology for the extremely narrow, single discharge pulses of the Charged Device Model. Human Body Model, Machine Model, Charged Device Model, Socket Device Model, Transmission Line Pulsing, impulse metrology, correlation, failure criteria, pico second

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oai:fraunhofer.de:N-106587Last time updated on 11/15/2016

This paper was published in Fraunhofer-ePrints.

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