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Reverse bias stress test of GaN HEMTs for high-voltage switching applications

By M. Dammann, H. Czap, J. Rüster, M. Baeumler, F. Gütle, P. Waltereit, F. Benkhelifa, R. Reiner, M. Cäsar, H. Konstanzer, S. Müller, R. Quay, M. Mikulla and O. Ambacher

Abstract

The degradation of packaged GaN HEMTs for high power applications has been studied under long term reverse bias step stress tests. Increases of leakage current and dynamic Ron resistance have been found. This degradation is possibly caused by the formation of localized defects which have been observed by backside electroluminescence imaging. In addition the effect of device layout and substrate material on the dynamic Ron as well as its temperature, recovery behavior, and drain voltage dependence have been investigated on wafer-level. The recovery behavior and the temperature dependence indicate that the dynamic Ron resistance increase is caused by surface or buffer carrier trapping. By reducing the buffer trap density the dynamic Ron resistance was reduced. A slightly higher dynamic Ron of GaN HEMTs on silicon compared to transistors on SiC substrate has been observed

Year: 2012
OAI identifier: oai:fraunhofer.de:N-227969
Provided by: Fraunhofer-ePrints
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