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C-NNAP - A parallel processing architecture for binary neural networks

By J.V. Kennedy, J. Austin, R. Pack and B. Cass

Abstract

This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations

Publisher: IEEE
Year: 1995
DOI identifier: 10.1109/ICNN.1995.487564
OAI identifier: oai:eprints.whiterose.ac.uk:1870

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