Skip to main content
Article thumbnail
Location of Repository

C-NNAP - A parallel processing architecture for binary neural networks

By J.V. Kennedy, J. Austin, R. Pack and B. Cass


This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations

Publisher: IEEE
Year: 1995
DOI identifier: 10.1109/ICNN.1995.487564
OAI identifier:

Suggested articles

To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.