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A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories

By C. Zambelli, M. Indaco, M. Fabiano, S. Di Carlo, P. Prinetto, P. Olivo and D. Bertozzi


In spite of the mature cell structure, the memory\ud controller architecture of Multi-level cell (MLC) NAND\ud Flash memories is evolving fast in an attempt to improve\ud the uncorrected/miscorrected bit error rate (UBER)\ud and to provide a more flexible usage model where the\ud performance-reliability trade-off point can be adjusted at\ud runtime. However, optimization techniques in the memory\ud controller architecture cannot avoid a strict trade-off between\ud UBER and read throughput. In this paper, we show\ud that co-optimizing ECC architecture configuration in the\ud memory controller with program algorithm selection at\ud the technology layer, a more flexible memory sub-system\ud arises, which is capable of unprecedented trade-offs points\ud between performance and reliability

Publisher: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Year: 2012
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