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Engineering Barrier and Buffer Layers in InGaAs Quantum-Well MOSFETs

By Luca Morassi, Giovanni Verzellesi, Zhao Han, Lee Jack C., Veksler Dmitry and Bersuker Gennadi

Abstract

Properties of InGaAs buried-channel quantum-well MOSFETs affected by the barrier and buffer layers are analyzed by numerical simulations to assist device engineering and optimization. The interplay between the charge-neutrality level position at the barrier/dielectric interface and conduction band discontinuity at the barrier/channel interface is shown to critically impact the achievement of an enhancement-mode device with full turn-on. A p-doped buffer is found to be a more suitable option than the standard unintentionally doped buffers to control short-channel effects

Topics: Buffer optimization, InGaAs, interface traps, III–V MOSFETs
Publisher: 'Institute of Electrical and Electronics Engineers (IEEE)'
Year: 2012
DOI identifier: 10.1109/TED.2012.2219534
OAI identifier: oai:iris.unimore.it:11380/902891
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