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A single-chip FPGA implementation of real-time adaptive background model

By Kofi Appiah and Andrew Hunter


This paper demonstrates the use of a single-chip\ud FPGA for the extraction of highly accurate background\ud models in real-time. The models are based\ud on 24-bit RGB values and 8-bit grayscale intensity\ud values. Three background models are presented, all\ud using a camcorder, single FPGA chip, four blocks\ud of RAM and a display unit. The architectures have\ud been implemented and tested using a Panasonic NVDS60B\ud digital video camera connected to a Celoxica\ud RC300 Prototyping Platform with a Xilinx Virtex\ud II XC2v6000 FPGA and 4 banks of onboard RAM.\ud The novel FPGA architecture presented has the advantages\ud of minimizing latency and the movement of\ud large datasets, by conducting time critical processes\ud on BlockRAM. The systems operate at clock rates\ud ranging from 57MHz to 65MHz and are capable\ud of performing pre-processing functions like temporal\ud low-pass filtering on standard frame size of 640X480\ud pixels at up to 210 frames per second

Topics: H670 Robotics and Cybernetics, G400 Computer Science
Publisher: IEEE
Year: 2005
DOI identifier: 10.1109/FPT.2005.1568531
OAI identifier: oai:eprints.lincoln.ac.uk:2800

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