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Easily testable carry-save multipliers with respect to path delay faults

By Th. Haniotakis, H.-T. Vergos, Y. Tsiatouhas, D. Nikolos and M. Nicolaidis


In this paper we propose the design of an easily testable, with respect to path delay faults, n*m carry-save multiplier (CSM) and give a path selection method such that all the selected paths for testing are Single Path Propagating Hazard Free Robustly Testable (SPP-HFRT). Only three additional test inputs are required while the hardware overhead is very small and the delay overhead negligible

Topics: carry-save-multipliers, path-delay-faults, path-selection-method, single-path-propagating-hazard-free-robustly-testable, SPP-HFRT, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Publisher: Slovak Univ. Technol, Bratislava, Slovakia
Year: 1999
OAI identifier: oai:HAL:hal-00013748v1
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