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WCET analysis of multi-level set-associative instruction caches

By Damien Hardy and Isabelle Puaut


With the advent of increasingly complex hardware in real-time embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), many processors now have a set-associative L2 cache. Thus, there is a need for considering cache hierarchies when validating the temporal behavior of real-time systems, in particular when estimating tasks' worst-case execution times (WCETs). To the best of our knowledge, there is only one approach for WCET estimation for systems with cache hierarchies [Mueller, 1997], which turns out to be unsafe for set-associative caches. In this paper, we highlight the conditions under which the approach described in [Mueller, 1997] is unsafe. A safe static instruction cache analysis method is then presented. Contrary to [Mueller, 1997] our method supports set-associative and fully associative caches. The proposed method is experimented on medium-size and large programs. We show that the method is most of the time tight. We further show that in all cases WCET estimations are much tighter when considering the cache hierarchy than when considering only the L1 cache. An evaluation of the analysis time is conducted, demonstrating that analysing the cache hierarchy has a reasonable computation time

Topics: WCET, hard real time systems, memory hierarchy, static analysis, abstract interpretation, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF]
Publisher: HAL CCSD
Year: 2008
OAI identifier: oai:HAL:inria-00286358v2

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