Skip to main content
Article thumbnail
Location of Repository

Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal–oxide–semiconductor field effect transistor channels

By T. J. Grasby, C. P. Parry, P. J. (Peter J.) Phillips, Barry M. McGregor, R. J. H. (Richard J. H.) Morris, Glyn Braithwaite, Terry E. Whall, Evan H. C. Parker, Richard Hammond, Andrew P. Knights and P. G. Coleman


Si/Si0.64Ge0.36/Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm2 V – 1 s – 1 for a sheet density of 6.2 × 1011 cm – 2. The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 °C, commensurate with metal–oxide–semiconductor device fabrication

Topics: TK, QC
Publisher: American Institute of Physics
Year: 1999
OAI identifier:

Suggested articles

To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.