Location of Repository

Single-Photon Avalanche Diodes (SPAD) in CMOS 0.35 µm technology

By D Pellion, K Jradi, Nicolas Brochard, D Prêle and Dominique Ginhac


International audienceSome decades ago single photon detection used to be the terrain of photomultiplier tube (PMT), thanks to its characteristics of sensitivity and speed. However, PMT has several disadvantages such as low quantum efficiency, overall dimensions, and cost, making them unsuitable for compact design of integrated systems. So, the past decade has seen a dramatic increase in interest in new integrated single-photon detectors called Single-Photon Avalanche Diodes (SPAD) or Geiger-mode APD. SPAD are working in avalanche mode above the breakdown level. When an incident photon is captured, a very fast avalanche is triggered, generating an easily detectable current pulse.This paper discusses SPAD detectors fabricated in a standard CMOS technology featuring both single-photon sensitivity, and excellent timing resolution, while guaranteeing a high integration. In this work, we investigate the design of SPAD detectors using the AMS 0.35 µm CMOS Opto technology. Indeed, such standard CMOS technology allows producing large surface (few mm2) of single photon sensitive detectors. Moreover, SPAD in CMOS technologies could be associated to electronic readout such as active quenching, digital to analog converter, memories and any specific processing required to build efficient calorimeters1 (Silicon PhotoMultiplier – SiPM) or high resolution imagers (SPAD imager). The present work investigates SPAD geometry. MOS transistor has been used instead of resistor to adjust the quenching resistance and find optimum value. From this first set of results, a detailed study of the dark count rate (DCR) has been conducted. Our results show a dark count rate increase with the size of the photodiodes and the temperature (at T=22.5 °C, the DCR of a 10 µm-photodiode is 2020 count s−1 while it is 270 count s−1 at T=−40 °C for a overvoltage of 800 mV). A small pixel size is desirable, because the DCR per unit area decreases with the pixel size. We also found that the adjustment of overvoltage is very sensitive and depends on the temperature. The temperature will be adjusted for the subsequent experiments

Topics: SPAD, CMOS 0.35 μm, DCR, Breakdown voltage, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing
Publisher: Elsevier
Year: 2015
DOI identifier: 10.1016/j.nima.2015.01.100
OAI identifier: oai:HAL:hal-01196570v1
Provided by: Hal-Diderot

Suggested articles


To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.