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Synthesis of reconfigurable multiplier blocks: part I: fundamentals

By Suleyman S. Demirsoy, Izzet Kale and Andrew G. Dempster

Abstract

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time multiplexed\ud implementation of multiple constant multiplications. This paper and its companion paper (subtitled Part II- Algorithm) together present a systematic synthesis\ud method for Single Input Single Output (SISO) and Single\ud Input Multiple Output (SIMO) ReMB designs. This paper\ud presents the necessary foundation and terminology needed for\ud developing a systematic synthesis technique. The companion\ud paper illustrates the synthesis method through examples. The\ud method proposed achieves reduced logic-depth and area over\ud standard multipliers / multiplier blocks

Topics: UOW3
Publisher: IEEE Computer Society
OAI identifier: oai:westminsterresearch.wmin.ac.uk:966
Provided by: WestminsterResearch

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Citations

  1. (1999). A new algorithm for elimination of common subexpressions”,
  2. (2003). Complexity Reduction in Digital Filters and Filter Banks”,
  3. (2003). Design Guidelines for Reconfigurable Multiplier Blocks”,
  4. (2002). Design of highspeed multiplierless filters using a nonrecursive signed common subexpression algorithm”,
  5. (2002). Extended results for minimum-adder constant integer multipliers”,
  6. (2002). Functionally diverse programmable logic implementations of digital signal processing algorithms”,
  7. (1995). General algorithms for reducedadder integer multiplier design”,
  8. (2001). Implementation of fixed DSP functions using the reduced coefficient multiplier”,
  9. (1995). Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters”,
  10. (1996). Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination”,
  11. (1986). Multiplication by integer constants”,
  12. (2001). Multiplier-less IIR filter Synthesis algorithms to trade-off the delay and the number of adders”,
  13. (1991). Primitive operator digital filters”,
  14. (2003). Reconfigurable implementation of recursive DCT kernels with reduced quantization noise”,
  15. (1996). Subexpression sharing in filters using canonic signed digit multipliers”,
  16. Synthesis of Reconfigurable Multiplier Blocks: Part II- Details of the Algorithm”, to be publised
  17. (1995). Use of minimum-adder multiplier-blocks in FIR digital filters”,

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