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A new bulk-driven input stage design for sub 1-volt CMOS op-amps

By Y. Haga, R.C.S. Morling and I. Kale


This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V/sub T0/+ 3V/sub DSsat/) to the maximum allowed for the CMOS process, as well as preventing latch-up

Topics: UOWSAT
Publisher: IEEE
Year: 2006
OAI identifier: oai:westminsterresearch.wmin.ac.uk:3340
Provided by: WestminsterResearch

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