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Serial Data concentrator in VHDL

By Tomáš Řeháček

Abstract

In the bachelor’s thesis text there are summarized basics of VHDL language, ISE Webpack development environment is described. Also the way of communication and properties of serial unit are described as well as Ethernet standard properties and the way of communication via MII interface. Hardware used for the data concentrator design is briefly introduced in the next part. At the end of the thesis there is analysis of the data concentrator design for data transmission from serial unit to Ethernet using protocols UDP/IP

Topics: MII; UDP; VHDL; CRC; serial communication; IPv4; datový koncentrátor; Ethernet; sériová komunikace; data concentrator
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Year: 2013
OAI identifier: oai:invenio.nusl.cz:243584
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