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Acceleration of Data Encryption Algorithms in FPGA

By Miroslav Gajdoš


This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue

Topics: acceleration; šifrovací algoritmus; VHDL; FPGA; encryption algorithm; DES; Spartan 3; Virtex 5.; akcelerace; FITkit
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Year: 2009
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