Skip to main content
Article thumbnail
Location of Repository

Acceleration of Data Encryption Algorithms in FPGA

By Miroslav Gajdoš

Abstract

This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue

Topics: acceleration; šifrovací algoritmus; VHDL; FPGA; encryption algorithm; DES; Spartan 3; Virtex 5.; akcelerace; FITkit
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Year: 2009
OAI identifier: oai:invenio.nusl.cz:237315
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://www.nusl.cz/ntk/nusl-23... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.