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Industrial HD camera interface

By Libor Juřica


Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring

Topics: slip ring; průmyslová kamera; FPGA; VHDL; komutátor; MGT; SDI; industrial camera
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Year: 2015
OAI identifier: oai:invenio.nusl.cz:221114
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