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Implementation of fast serial bus on FPGA

By Jakub Drbal

Abstract

This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources

Topics: differential signals; LVDS; FPGA; VHDL; diferenční signály; Serial bus; SATA.; Sériová sběrnice
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Year: 2014
OAI identifier: oai:invenio.nusl.cz:221037
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