Post-compilation analysis and power reduction

Abstract

Optimization outside of traditional frameworks is emerging as a new research focus in the compiler construction community. Scheduled assembly code is one area of increased interest. Optimization cannot be performed without a control-flow graph (CFG), and current CFG construction algorithms can fail on scheduled code. We present a new construction algorithm that correctly constructs CFGs and permits meaningful optimization for scheduled code. One potential post-compilation optimization is reducing power consumption by minimizing switching activity on the instruction bus. We designed and implemented an algorithm that attempts to minimize switching activity by renaming registers for Texas Instruments' TMS320C6200 processor. We gathered results using a power simulator developed inside Texas Instruments. We determine that reducing bit transitions on the instruction bus is not a profitable technique for reducing the power consumption of this particular microprocessor

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oai:scholarship.rice.edu:1911/17560Last time updated on 6/11/2012

This paper was published in DSpace at Rice University.

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