In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and\ud chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical\ud performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However,\ud utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased\ud heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the\ud cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture\ud necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their\ud design approach. Additional considerations include the effects due to temperature non-uniformity, localized\ud hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in electronic\ud chip cooling in the last decade and provides a vision for code signing integrated cooling systems. For various\ud heat fluxes on each side of a chip acting as discrete heat source, the current single-phase cooling technology is\ud projected to provide adequate cooling, albeit with high pressure drops. Effectively mitigating the high\ud temperatures surrounding local hot spots remains a challenging issue. Various forms of tabulators above the\ud chips, different geometric arrangements of the chips positioned top and bottom wall of the duct serves very\ud well in the heat augmentation technique with better performanc
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.