In the modern day digital systems, floating point units are an important component in many signal and image\ud processing applications. Many approaches of the floating point units have been proposed and compared with\ud their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for\ud floating point operations, single and double. In the proposed architecture double precision floating point unit is\ud used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high\ud speed adder, which is shared among other operations and can perform operations independently as a separate\ud unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing\ud technique which allows performing the operations with the minimum usage of the resources while computing\ud the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results\ud show the 23% improvement in the speed of the designed circuit
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