Skip to main content
Article thumbnail
Location of Repository

A Fast Floating Point Double Precision Implementation on Fpga

By Monika Maan and Abhay Bindal

Abstract

In the modern day digital systems, floating point units are an important component in many signal and image\ud processing applications. Many approaches of the floating point units have been proposed and compared with\ud their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for\ud floating point operations, single and double. In the proposed architecture double precision floating point unit is\ud used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high\ud speed adder, which is shared among other operations and can perform operations independently as a separate\ud unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing\ud technique which allows performing the operations with the minimum usage of the resources while computing\ud the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results\ud show the 23% improvement in the speed of the designed circuit

Topics: Carry Select Adder, Floating point unit, FPGA, IEEE-754 Standard, Reversible logic gates., Engineering (General). Civil engineering (General), TA1-2040, Technology, T
Publisher: International Journal of Engineering Research and Applications
Year: 2016
OAI identifier: oai:doaj.org/article:16acd6263f26417fa824f4d01f2d51e2
Journal:
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • https://doaj.org/toc/2248-9622 (external link)
  • https://doaj.org/toc/2248-9622 (external link)
  • http://www.ijera.com/papers/Vo... (external link)
  • https://doaj.org/article/16acd... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.