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Low voltage high performance hybrid full adder

By Pankaj Kumar and Rajender Kumar Sharma

Abstract

This paper presents a low voltage and high performance 1-bit full adder designed with an efficient internal logic structure that leads to have a reduced Power Delay Product (PDP). The modified NOR and NAND gates, an essential entity, are also presented. The circuit is designed with cadence virtuoso tool with UMC 90-nm and 55-nm CMOS technologies. The proposed adder is compared with some of the popular adders based on power consumption, speed and power delay product. The proposed full adder cells achieve 56% and 76.69% improvement in speed and power delay product metric when compared with conventional C-CMOS full adder. It is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages

Topics: High speed, Low voltage, Logic structure, Hybrid adder, Engineering (General). Civil engineering (General), TA1-2040
Publisher: Elsevier
Year: 2016
DOI identifier: 10.1016/j.jestch.2015.10.001
OAI identifier: oai:doaj.org/article:e1073a4161784fe79ea35935bd0513dc
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