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3-D Graphics Processor Unit with Cost-EffectiveRasterization Using Valid Screen Space Region

By Yeong-Kang Lai and Yu-Chieh Chung


In order to render 3-D graphics efficiently,rasterization techniques have been developed. Traditionalclipping techniques using six-planes of view volume arecomplicated and not cost-effective. This paper develops a novelcost-effective strategy for primitives with regard to clipping inrasterization. Throughout the process, no expensive clippingaction is required and no extra clipping-derived polygons areproduced. It also presents the architecture of a 200-MHz multicore,multi-thread 3-D graphics SoC in 65nm 1P9M processwith a core size of 4.97mm2 and 153.3mW for powerconsumption. The proposed clip-less architecture inrasterization processes the valid screen space region of eachprimitive in eight cycles, with a gate-count of only 20k. Inaddition, the throughput can achieve up to 25 M Triangles/Sec

Topics: 3-D graphics processor, rasterization
Year: 2014
DOI identifier: 10.1109/TCE.2013.6626259
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