System Analysis and Implementation of Delta-Sigma Modulator Topologies with Low Gain Amplifiers in 90nm CMOS


Data converters are one of the key components in many applications ranging from wireless communication to data acquisitions system, sensors, audio electronics, video display electronics and analog microcontrollers. All of these use some type of data converter to perform the task of signal processing/condition for example in RF transceivers the received analog signal after passing through filters is converted to digital signal for further processing. The use of delta-sigma modulators nowadays are gaining popularity over the other A/D converters because of sampling and noise shaping. Also the architecture of delta sigma modulator is a mixed system, and digital filters are present (to remove noise in case of MASH architecture) so because of these reason many programmable features can be used in the applications employing delta sigma modulator. This thesis presents a type of delta sigma modulator which focuses on using of low gain operational amplifier and hence to operate at low voltage technologies and be more power efficient. Two topologies were presented, one having a single loop architecture but with a very highly aggressive NTF and other using multi-stage architecture with no additional digital filter to achieve the required specifications. The thesis presents the complete system analysis of the topologies, and the non-idealities modeling at system level. Then the transistor level design of the designed topologies was done in Cadence in 90nm CMOS. Each component of the designed modulator was tested individually at circuit level. The complete system was analyzed using the Verilog-A model

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Publikationer från KTH

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