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Verification automatique des regles de dessin des circuits VLSI: regles formelles, approche hierarchique

By James S. Medou Zengue Ze

Abstract

SIGLEAvailable from INIST (FR), Document Supply Service, under shelf-number : T 79923 / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Topics: 09C - Electronic devices, electromechanical devices
Year: 1991
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Provided by: OpenGrey Repository
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