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Using the HDL-advisor for shortening the system design loop

By W. (Paderborn Univ. (Gesamthochschule) (Germany). Fachbereich 17 -Mathematik-Informatik) Hardt, J. Gerlach, H.J. Eikerling, W. (Tuebingen Univ. (Germany). Technische Informatik) Rosenstiel, CA (United States)) Mountain View Inc. B. (Synopsys Gregory and Verifikation dedizierte Anwendungen Test Synthese Technische Univ. Dresden (Germany). Sonderforschungsbereich 358 - Automatisierter Systementwurf

Abstract

In this paper, the integration of RT-level advice into the system-level synthesis methodology is examined. The synthesis procedure starts from a system-level specification given by standard C code. HW is extracted and synthesized by means of high-level synthesis. The result is a structural VHDL description. In order to shorten the design loop in a transformational synthesis environment, the task of conventional RT- and logic-level synthesis inside the optimization loop is replaced by an advice in order to predict the characteristics of the resulting circuit. As experimental results show, this enables the examination of a larger design space by reducing analysis time. (orig.)Available from TIB Hannover: RR 7264(96,6) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

Topics: 09H - Computer software, programming, LOGIC-LEVEL SYNTHESIS: M, DESIGN, RT-LEVEL, DISCRETE COSINE TRANSFORMATIONS, ADVICE TOOL, ESTIMATION TOOLS, SYSTEM-LEVEL
Year: 1996
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Provided by: OpenGrey Repository
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