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Verifying Relay Circuits using State Machines

By P.H.J. van Eijk


In this paper we present, illustrate and discuss a number of techniques that can be used\ud in the modelling and verification of electro-mechanical relay circuits. These techniques\ud are based on state machine descriptions of circuits and their functions, and on applying\ud validation tools for properties of such descriptions. In particular we have applied tools\ud that are based on the PROMELA language

Topics: Wijsbegeerte, formal specification, formal verification, safety critical system, relay, state machines, PROMELA
Year: 1997
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