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Implementace genetického algoritmu do obvodu FPGA

By Petr Burian

Abstract

This paper deals with the implementation of a standard genetic algorithm by an FPGA circuit. It examines the various features of this algorithm. The main goal of this work is building of an evolvable combinational circuit. Demands imposed on an FPGA circuit are researched as well

Topics: standardní genetický algoritmus, vyvíjející se obvody, standard genetic algorithm, evolvable hardware
Publisher: Západočeská univerzita v Plzni, Fakulta elektrotechnická
Year: 2008
OAI identifier: oai:dspace5.zcu.cz:11025/497
Journal:

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