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Error probability in synchronous digital circuits due to power supply noise

By Ferran Martorell Cid, Marc Pons Solé, Antonio Rubio and Francisco de Borja Moll Echeto

Abstract

This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.Peer Reviewe

Topics: Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats, Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals, Integrated circuits Very large scale integration, Integrated circuits Very large scale integration Reliability, Power supply noise, Error probability, CMOS synchronous circuits, Circuits digitals -- Disseny i construcció, Circuits integrats a molt gran escala -- Disseny i construcció
OAI identifier: oai:recercat.cat:2072/184768
Provided by: RECERCAT
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