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FPGA Implementation of Optimized 4 Bit BCD and Carry Skip Adders using Reversible Gates

By Manjula B.B, Venkatesh S .Sanganal, Hemalatha.K.N and Ravichandra V

Abstract

The project proposes design of BCD adder and implementation of Carry Skip adder using the new concept of Reversible logic gate to improve the design in terms of garbage’s and area on chip. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it’s zero power dissipation under ideal conditions. It is not possible to realize quantum computing without reversible logic gates. Thus, the project will provide the reversible logic implementation of the conventional BCD adder using NG and NTG gate and Carry skip adder using TSG. The proposed reversible logic implementation of the 4- bit BCD adder is optimized to obtain minimum number of reversible logic gates and minimum number of garbage outputs. This project work on the reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU. The designed and optimized 4-bit reversible BCD adder and existing Carry skip adder are implemented in VHDL Using Xilinx ISE 10.1 tool and simulated using ModelSim SE 6.3f. Implemented on FPGA Spartan-II

Topics: Reversible logic, Feyman gate, NOT Gate, Fredkin Gate, TSG Gate, New Toffoli Gate, New Toffoli Gate, TS-3 Gate, NTG, BCD etc., LCC:Electronic computers. Computer science, LCC:QA75.5-76.95, LCC:Instruments and machines, LCC:QA71-90, LCC:Mathematics, LCC:QA1-939, LCC:Science, LCC:Q, DOAJ:Computer Science, DOAJ:Technology and Engineering
Publisher: International Journal of Soft Computing & Engineering
Year: 2012
OAI identifier: oai:doaj.org/article:84d974bb33b94f128961d35efae957d1
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