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Aids—automatic synthesis, optimization

By Dong-u Lee, Altaf Abdul Gaffar, Oskar Mencer and Wayne Luk

Abstract

MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20 % and 12 % respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA

Topics: Algorithms, Design, Experimentation, Performance Keywords Affine Arithmetic, Bit-Width, Fixed-Point, FPGA, Simulated
Year: 2008
OAI identifier: oai:CiteSeerX.psu:10.1.1.67.1552
Provided by: CiteSeerX
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