Location of Repository

A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression

By Miguel Morales-s and Claudia Feregrino-uribe

Abstract

We present a hardware architecture that combines Elliptic Curve Cryptography (ECC) and lossless data compression in a single chip. Input data is compressed using a dictionary-based lossless data compressor before encryption, then; two elliptic curve cryptographic algorithms can be applied to the compressed data: ECIES for encryption or ECDSA for digital signature. Applying data compression presents three advantages: first, the improvement in the cryptographic module throughput by reducing the amount of data to be encrypted; second, the higher utilization of the available bandwidth if encrypted data is transmitted across a public network and third, the increment of the difficulty to recover the original information. The architecture was described in VHDL and synthesized for a Xilinx FPGA device. The results achieved show that it is possible to combine these two algorithms in a single chip while gathering the advantages of compression and cryptography. This work is novel in the sense that no such algorithm combination has been reported neither a hardware implementation of elliptic curve cryptographic schemes. 1

Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.418.3666
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://ccc.inaoep.mx/~cferegri... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.