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Partial order reduction for detecting safety and timing failures of timed circuits

By Denduang Pradubsuwun, Tomohiro Yoneda and Chris Myers

Abstract

Abstract. This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical verification. Experimenting with the STARI circuits, the proposed approach shows its effectiveness.

Year: 2005
OAI identifier: oai:CiteSeerX.psu:10.1.1.417.6346
Provided by: CiteSeerX
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