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Design of High Performance & Low Power Up Down Counter on FPGA Rajeev Kumar 1, Poonam Chauhan 2

By Mandeep Singh Saini

Abstract

Counters are the basic building block in embedded system design. Counters are used for counting purpose. Similarly it is used for frequency division.Counters are the Sequential Circuits in which the output depends upon the previous as well as present input. Basically counters are classified in two categories one is Asynchronous Counter and another is Synchronous Counter. The operation of the counter is depending upon the clock which is a timing signal. Clock is required to change the state of the counter i.e. triggering. For high speed (fast response) clock is taken as negative edge triggered. Counters are designed using flip flops that are the basic storage elements in digital design.A sequential circuit is the combination of Combinational circuit and Memory.The present input is stored in combinational circuit and the previous input is stored in memory. There are various types of counters such as Ripple Counter, Up Counter, Down Counter, Johnson Counter and Synchronous Counter. Here we present the design of 64bit up down counter & implementation is done on FPGA

Topics: Combinational Circuit, Sequential Circuit, Clock, Memory, FPGA Architecture Design
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.417.201
Provided by: CiteSeerX
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