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Design and Performance Analysis of Analog Sub circuits for Multiplying DAC used in Image Compression

By K. Satyanarayana Vittal, Dr. P. Cyril Prasanna Raj, Pillem Ramesh, B. V Aravind, Dr. Fazal, K. Satyanarayana Vittal, Dr. P. Cyril Prasanna Raj, Pillem Ramesh, B. V Aravind and Dr. Fazal Noorbasha

Abstract

Image compression is one of the prominent signal processing areas for multimedia applications. Compressed images when transmitted are affected by noise and thus reconstruction of images at the receiver becomes complex. Very recently Artificial Neural Networks are being used for image compression and decompression. One of the building blocks in ANN is the multiplying DAC. In this paper, we present the design and analysis of sub circuits for multiplying DAC using 180nm CMOS technology. The DA, current reference and opamp are design, modelled and analysed for its performances using Cadence Virtuoso and HSPICE. The optimum geometries for sub circuits are computed and schematic captured is carried out. The results obtained show that the designed sub circuits are suitable for multiplying DAC implementation

Topics: Artificial Neural Networks, Synapse Threshold Logic Unit (TLU) proposed by Warren McCulloch and Walter Pitts in 1943
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.416.9891
Provided by: CiteSeerX
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