Skip to main content
Article thumbnail
Location of Repository

New Design of High Performance 2:1 Multiplexer

By Ila Gupta, Neha Arora, Prof B. P. Singh and Lakshmangarh Lakshmangarh Lakshmangarh

Abstract

Recently low power circuits have become a top priority in modern VLSI design. This paper presents post layout simulations of a new improved 2:1 multiplexer design. The proposed design demonstrates its superiority against existing 2:1 multiplexer design in terms of power–delay product (PDP), temperature sustainability, noise immunity and frequency. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13.

Topics: 2, 1 multiplexer, low power, power consumption
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.416.8113
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.ijera.com/papers/Vo... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.