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New Design of High Performance 2:1 Multiplexer

By Ila Gupta, Neha Arora, Prof B. P. Singh and Lakshmangarh Lakshmangarh Lakshmangarh


Recently low power circuits have become a top priority in modern VLSI design. This paper presents post layout simulations of a new improved 2:1 multiplexer design. The proposed design demonstrates its superiority against existing 2:1 multiplexer design in terms of power–delay product (PDP), temperature sustainability, noise immunity and frequency. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13.

Topics: 2, 1 multiplexer, low power, power consumption
Year: 2014
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