Skip to main content
Article thumbnail
Location of Repository

Design Of Adiabatic Logic Based Low Power Carry Select Adder

By P. Ashok Kumar and B. Vijaya Bhaskhar

Abstract

Adders are of fundamental importance in a wide variety of digital systems. Many fast adders exist, but adding fast using low area and power is still challenging. This paper presents a new bit block structure that computes propagate signals called “carry strength ” in a ripple fashion. Several new adders based on the new carry select Adder structure are proposed. Comparison with wellknown conventional adders demonstrates that the usage of carry-strength signals allows high-speed adders to be realised at significantly lower cost and consuming lower power than previously possible. As well as in this paper we are concentrating on the heat dissipation & we are reducing the current using adiabatic logic

Topics: Application Specific Integrated Circuit (ASIC, Area Efficient, CSLA, Low Power
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.416.1863
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.ijera.com/papers/Vo... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.