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Design Of Adiabatic Logic Based Low Power Carry Select Adder

By P. Ashok Kumar and B. Vijaya Bhaskhar

Abstract

Adders are of fundamental importance in a wide variety of digital systems. Many fast adders exist, but adding fast using low area and power is still challenging. This paper presents a new bit block structure that computes propagate signals called “carry strength ” in a ripple fashion. Several new adders based on the new carry select Adder structure are proposed. Comparison with wellknown conventional adders demonstrates that the usage of carry-strength signals allows high-speed adders to be realised at significantly lower cost and consuming lower power than previously possible. As well as in this paper we are concentrating on the heat dissipation & we are reducing the current using adiabatic logic

Topics: Application Specific Integrated Circuit (ASIC, Area Efficient, CSLA, Low Power
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.416.1863
Provided by: CiteSeerX
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