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Incremental elaboration for run-time reconfigurable hardware designs

By Arran Derbyshire, Tobias Becker and Wayne Luk

Abstract

We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher flexibility than ASICs. The compilation of hardware during run time, however, can add significant runtime overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching

Topics: Design, Theory Keywords Incremental elaboration, run-time reconfiguration, hardware compilation
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.415.8083
Provided by: CiteSeerX
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