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I 2 SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems

By Manhee Lee, Minseon Ahn and Eun Jung Kim

Abstract

Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure memory and cache-to-cache communications in shared memory multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coherence protocols, we refer to it as Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems (I 2 SEMS). The main challenge in designing I 2 SEMS is how to precompute keystreams in a timely manner, which is critical to minimize performance overhead. We achieve this goal by adopting a single system-wide Global Counter Controller (GCC) and three additional components for each processor: a keystream queue, a keystream cache, and a keystream pool. The GCC assigns a unique range of counters as a way to help processors precompute the counters ’ keystreams. We have implemented I 2 SEMS using Simics with Wisconsin multifacet General Execution-driven Multiprocessor Simulator (GEMS). We tested our design with SPLASH-2 benchmarks on up to 16-processor shared memory multiprocessor systems. Simulation results show that the overall performance slowdown is 4 % on average and the keystream hit rate is as high as 78%. The stable keystream hit rate shows that I 2 SEMS works well with both memory-read and memory-write dominant applications. Similar to the conventional cache, a large keystream pool size is beneficial to high hit rates.

Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.414.1930
Provided by: CiteSeerX
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